Chip/VLSI Design

Dear Sirs,

I am an experienced chip professional with more than 8 years of design career. I am particularly specialized in FPGA, ASIC and SOC design and I am also skilled at designing mixed analog, digital circuits and asynchronous cisrcuits. Since 2006 I entered into the VLSI industry at several semiconductor corporations and design firms and have designed numerous chips in various industry fields for a number of clients. As a result I am familiar with the entire design process and methodologies, particularly the back end layout design - partitioning, floorplanning, placement and routing. I am well acquainted with major placement and routing algorithms and I am also experienced with the mainstream CAD/EDA tools such as those from Cadence, Mentor, Synopsys, SPICE etc. I am also in good command of Verilog/ VHDL.

I am also very much interested in chip design related math and algorithms and I am currently focusing on the graph theoretical and combinatorial algorithms for the promising VLSI technologies such as FPGA, SOC, NOC, 3D (three dimensional) , and reconfigurable computing.

As a master of science of one of the top universities in China and as a PhD candidate of several top world universities, I possess sound foundation of semiconductor physics as well as basics of analog and digital ICs and components. I am familiar with the semiconductor components and CMOS processing technologies as well.

English has been my working language for many years and hence my proficiency of English is at the native level. German as well as French, is also among my linguistic menu along with several other less skilled languages such as Russian and Greek. I used to be one of the key personnel in multinationals of other, non-silicon industries.

I pretty much enjoy team work and with my own group of IC engineers I am enjoying a career and life which only the happiest folks in the world may share. Therefore I would like very much to share my joy with you as well, while delivering my excellent chip expertise.

Yours sincerely,

Mark Chen

经理先生，您好！

很高兴与您联系关于承接芯片（数字与模拟集成电路）布局（Layout）/ 版图 / 后端设计的工作。

本人同济大学硕士毕业，具备扎实的半导体物理理论基础，以及良好的模拟和数字集成电路及元器件的基础, 熟练掌握模拟电路和数字电路设计技术， 熟悉半导体器件及CMOS的工艺及制程。

本人自2006年开始进入芯片设计行业， 有多个芯片公司设计工作经历，特别擅长数字和模拟集成电路版图设计；熟悉版图设计各个环节的工作特点，工作计划的制定过程；熟练掌握集成电路版图设计方法（高精度匹配，寄生参数优化等）；熟悉版图的设计要求和技巧；熟悉版图层次结构；熟悉后端设计的完整设计流程，了解设计规则并能熟练进行验证及修改。

本人参与过数字与模拟芯片产品的全面开发工作, 懂得布局布线并能根据前端的线路设计要求独立完成顶层/模块； 实现顶层/模块级版图规划, 设计, 集成 等。 掌握ASIC设计Sign-off的步骤和流程, 完成从逻辑综合后网表到芯片Tape-out全过程; 熟悉诸如布局布线、版图、静态时序分析Timing closure 、时序库和物理库的建立，电源分析、信号完整性分析，寄生参数提取和物理验证要求等后端相关工作； 熟悉I/O pad, Satandard Cell, Rom等版图。 本人有基本的floorplan概念，具备P&R的基础，熟练使用P&R工具。

本人能编写约束文件，使用主流EDA工具进行RTL综合，评估代码性能、面积、功耗；本人也能独立解决DRC和LVS遇到的问题。

本人有流片和产品的经验，能根据不同代工厂的要求进行mask job view；能够独立完成数据库的转换、协助有关部门进行流片 。

本人比较理解芯片生产工艺规则，并能根据需要做适当调整和改动， 完成设计文件归档，撰写芯片设计、测试报告，协助测试工程师进行中测和成测规范的定义及其验证。

本人尤其熟悉FPGA的设计技术，比较专注此类芯片的设计。

本人也掌握Verilog/ VHDL 语言编程技术；能依据数字前端工程师的Verilog/ VHDL算法代码实现数字IC从RTL到GDS的相关设计。

本人具有丰富的CAD/EDA设计经验， 精通主要的版图设计和验证软件工具，例如Cadence，Mentor ，Synopsys 等。

除别人以外， 还有一个大约5人的芯片发烧友可以合作， 一起参与到芯片设计项目中。

此外，本人熟悉许多其它必要的的IT技术， 包括能够熟练使用UNIX/Linux、shell/perl/python/C/C++，处理器指令集（汇编语言） 等语言。

外语方面： 我过去在多个跨国公司有多年的工作经验，包括芯片设计的经验， 外语水平优秀，英语水平几乎达到与汉语相当的程度。另外还熟悉德语，法语等其他几门外语。

如果以上这些还不是主要的话， 最关键的是，我的毅力，克服困难的能力，对工作的高度热情， 卓越的学习能力和独立解决问题的能力。这些素质使得我能面对新问题，找到解决办法， 而不论从事何种工作。

致礼！

陈明华

注： 若有合作机会， 将进一步进行商讨。